1. Field of the Invention
The present invention relates to driver circuits which output signals at high speed and, particularly, to a low-voltage differential signaling (LVDS) driver circuit and a driver circuit which provide logic output and high impedance output.
2. Description of Related Art
Higher-speed and lower-voltage data transmission between large scale integrations (LSIs) has been developed recently. In such transmission systems, LSIs using a LVDS circuit are often used for LCD drivers and so on. Further, improved LVDS circuits are used for IEEE 1394.a standard of transmission system.
While an output voltage magnitude of conventional complementary metal-oxide semiconductor (CMOS) circuits is normally a power supply voltage, that of the LVDS circuit is as low as about 0.3V. Reduction of the output voltage magnitude of data output gives significant advantages such as higher transmission speed, lower power consumption, less noise in signal transmission, and higher external noise resistance.
Various approaches for LVDS driver circuits to output the low output voltage magnitude reliably at high speed have been proposed. The technique disclosed in Japanese Unexamined Patent Application Publication No. 2001-085977, a first conventional art, is shown in FIG. 5. This conventional LVDS driver circuit includes a first current switch circuit having transistors Qp11 and Qn11, a second current switch circuit having transistors Qp12 and Qn12, and a third current switch circuit having transistors Qp13 and Qn13, which are connected between a current source Qp14 at the side of a supply voltage Vcc and a current source Qn14 at the side of ground GND.
The first current switch circuit switches in such a way that one output terminal is connected either the current source Qp14 or Qn14 according to a non-inverted input signal IN11. The second current switch circuit switches in such a way that the other output terminal is connected either the current source Qp14 or Qn14 according to an inverted input signal IN12. A pair of output terminals output a pair of output signals OUT1 and OUT2. The third current switch circuit switches in such a way that a capacitor C11 is connected either the current source Qp14 or Qn14 according to the non-inverted input signal IN11
A time difference between the input of the non-inverted input signal IN11 and the input of the inverted input signal IN12 causes insufficient logic output voltage magnitude. To overcome this problem, this LVDS driver circuit has the third current switch circuit so as to correct the time difference between the non-inverted and inverted input signals, thereby obtaining a desired logic output voltage magnitude.
Japanese Unexamined Patent Application Publication No. 2000-174605, a second conventional art, discloses a technique to eliminate noise on output signals generated in the transition from a high impedance output state to a logic output state in the LVDS circuit which provides logic output and high impedance output. FIG. 6 shows the circuit structure of this conventional technique. A bypass circuit composed of transistors P27 and N27 is added to a normal LVDS driver circuit. In thins circuit, an input signal is inputted to a switching voltage generator circuit, which is not shown, so that the switching voltage generator circuit turns on and off transistors P23, P24, N23, and N24 according to the input signal.
The operation of the above circuits is explained below with reference to timing charts shown in FIG. 7A to 7C. FIG. 7A is a timing chart of a normal LVDS driver circuit with no bypass circuit. In the LVDS driver circuit having no bypass circuit, an inverted enable signal ENB is inputted to a switching voltage generator circuit. The switching voltage generator circuit outputs signals APA, APB, ANA, and ANB. The conductive state of transistors P23, P24, N23, and N24 is controlled according to the signals APA, APB, ANA, and ANB. In this example, if the inverted enable signal ENB is High and the output is high impedance, the transistors P23, P24, N23, and N24 are all off, and nodes P and N are at a power supply voltage VDD and a ground voltage GND, respectively. If, then, the inverted enable signal ENB turns to Low and the circuit outputs a logic level, the transistors P23, P24, N23, and N24 turn on or off to provide a logic output in accordance with input data. In the logic output state, the node P is at a slightly higher voltage than High level, while the node N is at a slightly lower voltage than Low level.
Since the node P is at the power supply voltage VDD in the first logic output immediately after the inverted enable signal ENB is changed from High to Low, the output High level has a significant overshoot waveform due to the power supply voltage of the node P. On the other hand, since the node N is at the ground voltage GND, the output Low level has a significant undershoot waveform due to the ground voltage of the node N. Thus, the output waveforms initially swing largely and are thereby distorted greatly as shown in FIG. 7A.
To overcome the above problem, the circuit of FIG. 6 has the bypass circuit including the transistors P27 and N27 so that a current keep flowing between the nodes P and N during the high impedance output. The voltages on the nodes P and N in the high impedance output state are thereby substantially equal to those in the logic output state, which creates proper output waveforms as shown in FIG. 7B.
The bypass circuit in the circuit of FIG. 6 is, however, designed to work with a predetermined particular termination voltage. Thus, if a termination voltage different from the predetermined voltage is used, the problem of distortion of output waveform cannot be overcome with the technique of the second conventional art but remains unsolved. FIG. 7C shows the case where a voltage VTT11 which is higher than a predetermined termination voltage VTT is used as a termination voltage. In the high impedance output, the voltages of the nodes P and N are set to depend on the predetermined termination voltage VTT. On the other hand, in the logic output after the inverted enable signal ENB turns to Low level, the voltages of the nodes P and N depend on a connected termination voltage VTT11 (VTT<VTT11); as a result, they increase by ΔV=VTT11−VTT. The change in the voltages of the nodes P and N causes the output waveforms to be distorted, which does not allow for the faster data transmission. The technique disclosed in the second conventional art does not accept the use of a different termination voltage level.
The problem to be solved in the present invention is that the above-described conventional LVDS driver circuit works only with a particular termination voltage, and the use of a different termination voltage causes a voltage to change by a difference in the termination voltages, which distorts the output waveform, thus not achieving high-speed data transmission.